Conventionally, a leadless semiconductor device such as a QFN (Quad Flat No Lead) is known as a semiconductor device that includes a lead frame, for example. In such a semiconductor device, recently, it is required to increase the number of terminals, and in response to this, the terminals are provided in a plurality of columns or the like.
However, in order to provide the terminals in a plurality of columns, it is necessary to provide wirings with a narrow pitch. The wirings of the lead frame are formed by penetrating a metal plate from upper and lower surfaces by etching. As the etching proceeds, not only in a depth direction, in a width direction as well, if the metal plate is thick, the space between the wirings becomes broad, and the wirings cannot be provided with a narrow pitch. Thus, conventionally, a metal plate with a thickness of about 0.2 mm is used. However, in order to provide the wirings with a narrower pitch, it has been studied to use a thinner metal plate.
However, if the wirings are formed by etching a thin metal plate, a risk that the wirings are deformed increases. Thus, it is difficult to actualize a lead frame that uses a metal plate thinner than a certain level.
Patent Document 1: Japanese Laid-open Patent Publication No. 2000-307049